With increasing demand for miniaturization, thinness, and high integration of electronic components, there is a growing demand for semiconductor package area and package thickness reductions. Typical packaging methods utilize wire bonding technology, in order to achieve leading out of chip electrodes or input/output terminals. Although this type of packaging technology is mature and relatively easy to produce, the height of the wire can be significantly higher than the height of the chip, such that the thickness of the chip package is increased along with the package area. In order to reduce the thickness/area of the chip package, flip-chip packaging technology is widely used.